Συντάχθηκε 11-01-2012 14:28
από Galateia Malandraki
Email συντάκτη: gmalandraki<στο>tuc.gr
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Ιδιότητα: υπάλληλος ΑΡΜΗΧ.
ΠΟΛΥΤΕΧΝΕΙΟ ΚΡΗΤΗΣ
Τμήμα Ηλεκτρονικών Μηχανικών και Μηχανικών Υπολογιστών
ΠΑΡΟΥΣΙΑΣΗ ΔΙΔΑΚΤΟΡΙΚΗΣ ΔΙΑΤΡΙΒΗΣ
“ARCHITECTURAL TRADE-OFFS OF PARTIAL RECONFIGURATION IN FPGA SYSTEMS”
Κυπριανός Δ. Παπαδημητρίου
Παρασκευή 13 Ιανουαρίου 2012, Ώρα 15:00
Κτίριο Επιστημών, Αίθουσα 145-Π58 (2ος όροφος), Πολυτεχνειούπολη
Εξεταστική Επιτροπή:
Καθηγητής Απόστολος Δόλλας (επιβλέπων), Τμήμα ΗΜΜΥ - Πολυτεχνείου Κρήτης
Καθηγητής Κωνσταντίνος Καλαϊτζάκης, Τμήμα ΗΜΜΥ - Πολυτεχνείου Κρήτης
Καθηγητής Διονύσιος Πνευματικάτος, Τμήμα ΗΜΜΥ - Πολυτεχνείου Κρήτης
Καθηγητής Γεώργιος Σταυρακάκης, Τμήμα ΗΜΜΥ - Πολυτεχνείου Κρήτης
Καθηγητής Μανόλης Κατεβαίνης, Τμήμα Επιστήμης Υπολογιστών - Πανεπιστημίου Κρήτης
Καθηγητής Γεώργιος Σταμούλης, Τμήμα Μηχανικών Η/Υ, Τηλεπικοινωνιών και Δικτύων - Πανεπιστημίου Θεσσαλίας
Αν. Καθηγητής Ιωάννης Παπαευσταθίου, Τμήμα ΗΜΜΥ - Πολυτεχνείου Κρήτης
ΠΕΡΙΛΗΨΗ
Reconfigurable computing (RC) is increasingly gaining the attention of many researchers and users by the academia and industry alike. The most popular representatives of reconfigurable computing are Field Programmable Gate Arrays (FPGAs). FPGAs are integrated circuits consisting of a large array of uncommitted programmable logic and interconnect, plus large blocks such as memories and Digital Dignal Processing (DSP) units that can be configured to implement digital circuits. Their capability to be programmed and re-programmed in the field, i.e. forming on demand the digital circuit that will execute the application at hand, offers an unprecedented advantage over other technologies such as the Application Specific Integrated Circuits (ASICs) that cannot be reprogrammed, and the traditional software microprocessors in which flexibility comes at the expense of limited performance due to the fixed instruction set and the lack of parallelism. Moreover, GPUs that have started to be used for accelerating computationally intensive applications, although stand as strong opponents to the FPGAs, they have fixed hardware resources that cannot be customized to the application at hand.
An important portion of the FPGA market concerns static RAM (SRAM) based FPGAs, meaning that the SRAM bits are connected to the configuration points in the chip, and programming the SRAM bits configures the chip. A promising feature of specific families of SRAM-based FPGAs is the ability to reuse the same hardware for different tasks at different phases of an application execution. Moreover, the tasks can be swapped on the fly while part of the hardware continues to operate. This feature is known as run-time or dynamic reconfiguration.
Building upon the idea of dynamically reconfiguring a circuit in SRAM-based FPGAs, this dissertation explores the architectural tradeoffs of implementing applications in partially reconfigurable (PR) FPGA-based systems and proposes new avenues for its use. The dissertation begins with an in-depth study of the literature on reconfigurable devices and concentrates on those that can be configured in part. Next, it proposes a novel way to schedule tasks in PR FPGAs which is evaluated within the context of a simulation framework. Then, a real-world experimental framework allowing to study the functional details of reconfiguration is presented. Using this framework a theoretical model is shaped which can be used for the early assessment of the overhead that the reconfiguration process incurs to the application execution. Finally, the dissertation proposes a novel way to exploit the PR technology in a specific application domain. In particular, a new method based on the PR capability of specific FPGAs is described, which allows for the self-repairing of FPGA core while operating in a harsh environment. All aspects of the present research have been verified with experiments from different setups using partially reconfigurable FPGA platforms.
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ΑΝΑΚΟΙΝΩΣΗ ΔΙΔΑΚΤΟΡΙΚΟΥ - ΠΑΠΑΔΗΜΗΤΡΙΟΥ.docx
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