Συντάχθηκε 13-04-2011 14:11
από Eleni Stamataki
Email συντάκτη: estamataki<στο>tuc.gr
Ενημερώθηκε:
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Ιδιότητα: σύνταξη/αποχώρηση υπάλληλος.
ΠΟΛΥΤΕΧΝΕΙΟ ΚΡΗΤΗΣ
Τμήμα Ηλεκτρονικών Μηχανικών και Μηχανικών Υπολογιστών
ΠΑΡΟΥΣΙΑΣΗ ΔΙΔΑΚΤΟΡΙΚΗΣ ΔΙΑΤΡΙΒΗΣ
“Novel Techniques for Hardware/Software
Partitioning and Emulation”
Μαυροειδής Ιάκωβος
Παρασκευή 15 Απριλίου 2011, Ώρα 16:00
Αμφιθέατρο Κτ. Επιστημών, Πολυτεχνειούπολη
Εξεταστική Επιτροπή: Επ. Καθ. Ιωάννης Παπαευσταθίου, Τμήμα ΗΜΜΥ, Πολυτεχνείου Κρήτης (επιβλέπων)
Καθ. Απόστολος Δόλλας, Τμήμα ΗΜΜΥ, Πολυτεχνείου Κρήτης
Καθ. Διονύσιος Πνευματικάτος, Τμήμα ΗΜΜΥ, Πολυτεχνείου Κρήτης
Καθ. Εμμανουήλ Κατεβαίνης, Τμήμα Επιστήμης Υπολογιστών, Πανεπιστημίου Κρήτης
Καθ. Κωνσταντίνος Καλαϊτζάκης, Τμήμα ΗΜΜΥ, Πολυτεχνείου Κρήτης
Αν. Καθ. Δημήτριος Γκιζόπουλος, Τμήμα Πληροφορικής, Πανεπιστημίου Πειραιώς
Επ. Καθ. Δημήτριος Σούντρης, Σχολή ΗΜΜΥ, Εθνικού Μετσόβιου Πολυτεχνείου
ΠΕΡΙΛΗΨΗ
Over the last several years, uniprocessor systems, in an effort to overcome the limits of deeper pipelining and instruction-level parallelism, evolved from one processing core to tens or hundreds of cores. At the same time, multi-chip systems and Systems on Board (SoB), have started giving their place to Systems on Chip (SoC) that exploit the latest nanometer technologies. This has also caused a tremendous shift in the system development process towards embedded systems, hardware/software co-design, SoC designs, multi-core designs, and hardware accelerators. Nowadays, one of the key issues for continued performance scaling is the development of advanced CAD tools that can efficiently support the design and verification of these new platforms and the requirements of today’s complex applications.
This thesis focuses on three important aspects of the system development process: hardware/software partitioning, simulation and verification. Since the time consumed in those tasks is usually a large percentage of the overall development time, speeding them up can significantly reduce the ever important time to market.
Hardware emulation on FPGAs has been widely used as a significantly faster and more accurate approach for the verification of complex designs than software simulation. In this approach, Hardware Simulation Accelerator and Emulator co-processor units are used to offload calculation-intensive tasks from software simulators. One of the biggest problems however is that the communication overhead between the software simulator, where the behavioral testbench usually runs, and the hardware emulator where the Design Under Test (DUT) is emulated, is becoming a new critical bottleneck. Another problem is that in a hardware emulation environment it is impossible to bring outside of the chip a large number of internal signals for verification purposes. Therefore, on-chip observability has become a significant issue. Finally, one more crucial issue is the decision that has to be made on how to partition the system components into two distinct sets: those that will be implemented in hardware and those that will run in software. In this thesis we analyze all the aforementioned problems and propose novel techniques that can be used to attack them.
First, we introduce a novel emulation framework that automatically transforms certain HDL parts of the testbench into synthesizable code in order to offload them from the software simulator and, more importantly, minimize the aforementioned communication overhead. Next, we extend this architecture by adding multiple fast scan-chain paths in the design in order to provide full circuit observability and controllability on the fly. Finally, we develop a fully automated hardware/software partitioning tool that incorporates a novel flow with new cost metrics and functions to provide fast and efficient solutions. The tool employs two separate partitioning algorithms; Simulated Annealing (SA) and a novel greedy algorithm, the Grouping Mapping Partitioning (GMP).
Our experiments demonstrate that our methodologies provide cost-effective solutions for the hardware/software partitioning and emulation of large and complex systems.
