Συντάχθηκε 14-10-2014 14:17
από Esthir Gelasaki
Email συντάκτη: egelasaki<στο>tuc.gr
Ενημερώθηκε:
-
Ιδιότητα: υπάλληλος.
ΠΟΛΥΤΕΧΝΕΙΟ ΚΡΗΤΗΣ
Σχολή Ηλεκτρονικών Μηχανικών και Μηχανικών Υπολογιστών
Πρόγραμμα Προπτυχιακών Σπουδών
ΠΑΡΟΥΣΙΑΣΗ ΔΙΠΛΩΜΑΤΙΚΗΣ ΕΡΓΑΣΙΑΣ
ΠΑΥΛΟΥ ΓΙΑΚΟΥΜΑΚΗ
με θέμα
Εξόρυξη Δεδομένων από Ροές με Χρήση Αναδιατασσόμενης Λογικής
FPGA-based Data Mining from Streams
Τετάρτη 15 Οκτωβρίου 2014, 13:30
Αίθουσα 145.Π42, Κτίριο Επιστημών, Πολυτεχνειούπολη
Εξεταστική Επιτροπή
Καθηγητής Κοσμήτορας της Σχολής Απόστολος Δόλλας (επιβλέπων)
Αναπληρωτής Καθηγητής Γιάννης Παπαευσταθίου
Καθηγητής Μίνως Γαροφαλάκης
Περίληψη
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Abstract
Data Stream Mining is a relatively new field of Data Mining and Hoeffding trees is a very popular classification algorithm on streaming data (instances). The basic Hoeffding tree algorithm, with some extensions, was originally presented as VFDT (Very Fast Decision Trees) by Domingos and Hulten.
We studied Hoeffding trees and the most of its available extensions. There is a large number of customizations and that makes it hard to study them all and select a ``good case'' to be implemented and optimized in custom hardware. Nevertheless, we found that the main behavior of the algorithm remains similar. Thus, we selected a configuration very close to the initial VFDT algorithm.
Hoeffding Trees are highly parallelizable and employ operations on the leaves that seem to fit well on FPGAs. We designed a simple processing unit (the Attribute Processor - AP) that could be used by very small embedded systems, and is capable of updating a leaf and computing the best (binary) split suggestions, using negligible resources.
By using a group of APs we designed the Attribute Processing Array (APA). It can easily take full advantage of the bandwidth of a single memory controller port (in our case the Convey Coprocessor MC port) with very low resources.
To exploit the processing power of Convey's HC-2ex we had to make a clever partitioning between hardware and software by selecting a custom instruction set and designing a collection of ``utility'' hardware modules, that all together compose an interesting architecture.
